In the procedure of processor development, functional verification is a crucial step that should be conducted before physical implementation. The purpose of processor functional verification is to determine, via simulation, that if the designed processor (in the form of HDL source code) can carry out its supported instructions as ISA specified. To perform processor functional verification, you will need to prepare the suite of test cases using the instructions supported by processor. Each test case has its purpose and its binary format (machine code) will be stored in the processor’s instruction memory. The processor to be tested (again, in the form of HDL source code) will then carry out the test case code under the control of a software testbench, which is responsible to start/stop the test, and report pass/failure of the test. As an ex, a sample MIPS processor test case is shown in Attachment 1
prepare a suite of test cases to verify the carrying out of following MIPS instructions:
ADD, SUB, AND, OR, SLT, LW, SW, BEQ, J, ADDI, MULT, MFHI, MFLO, JR, JAL, LUI, NOR, XOR, SLL, SLLV, SRA, SRAV, SRL, SRLV, and DIV.
Note that this is an open-ended project. You will be given extra credit by doing following:
1) Showing good verification strategy,
2) Covering more instructions specified by the MIPS ISA.
Composite, ad hoc testing – addi, add, sub, and, or, slt, beq, j, lw, sw
The MIPS processor prepares the value 7 in address 84 of the data memory.