For each of the following counters, determine the sequence that the counter will generate when triggered by a clock. Draw a state diagram and the output waveforms that show all the states. Assume that all flip-flops are initially in the reset state and that they are triggered on the rising edge of the clock signal. FF0 is the least significant bit.

For each counter you design create appropriate waveforms, state tables, Boolean expressions, and logic diagrams. Assume all counters start in state 0. Design counters that meet each of the following specifications:

3. Design a 3-bit synchronous counter where each new state is the previous state plus 3 modulus 8: (previous state + 3) mod 8. (The modulus operation returns the remainder after division. 9 mod 8 = 1). That is the states are:

0→3→6→1→4→7→2→5

4. Design a 3-bit synchronous counter whose states are 0 and the prime numbers lessthan 8 (in ascending order).