Write a VHDL module to implement an 8-bit serial-in, serial-out right-left shift register with inputs RSI, LSI, En, R, and Clk. RSO and LSO are the serial outputs, so they should be the rightmost and leftmost bits of the register. However, the values of the other flip-flops inside the register should not appear on the outputs. When En = 1, at the rising edge of the clock, the register shifts right if R = 1or left if R = o.RSI should be the shift-in input if R = 1, and LSI should be the shift-in input if R = o. When En = o, the register holds its state.There should also be an asynchronous active-low clear input ClrN.