Computer Systems and Networks Assignment-

Software requirement: You must use the Logisim simulator to create your circuits.

Task Description: You are to build (and test) the following digital logic circuit in the Logisim simulator and write a short report that describes your circuit. The maximum mark that you are able to achieve on the assignment will be determined by the difficulty of the circuit you decide to build (Option 1 or Option 2, see below).

Circuit Options:

OPTION1: Part A only

OPTION2: Part A and Part B

Requirements:

For this assignment you are required to implement a simple key and lock mechanism. The key will be an octal digit (3 input bits, values 0..7). The lock will also be an octal digit (3 input bits, values 0..7). The key will fit the lock if its octal digit matches the octal digit of the lock.

Example 1: Key is 2 and Lock is 7. The numbers (2 and 7) do not match, the key does not unlock the lock.

Example 2: Key is 6 and lock is 3. The numbers (6 and 3) do not match, the key does not unlock the lock.

Example 3: Key is 5 and lock is 5. The numbers (5 and 5) match, the key unlocks the lock.

Note: These are just a couple of examples. There are more cases that result in the key unlocking the lock or failing to unlock the lock. Your circuit must correctly unlock or keep the lock locked for all cases.

For this assignment, the key will be represented by three inputs (3 bits). The three key inputs are named as K1, K2, and K3. The table below shows the assignment of bits to each key value for K1, K2, and K3.

Key Inputs

For this assignment, the lock will be represented by three inputs (3 bits). The three lock inputs are named as L1, L2, and L3. The table below shows the assignment of bits to each lock value for L1, L2, and L3.

Lock Inputs

Part A- Circuit Option 1: Part A Only:

The implementation for this part must use only the three basic logic gates (AND, OR, NOT) with maximum 2 inputs.

You are required to implement a circuit where the user (you) can input a key value (K1, K2, and K3) and a lock value (L1, L2, and L3) and the circuit decodes the K1, K2, K3 and L1, L2, L3 values using a decoder (see lecture notes) as well as other permitted logic gates to determine if the key matches the lock.

The output will be a single LED labelled OPEN which is lit if the key matches the lock, and is not lit if the key and lock are different.

Part B- Circuit Option 2: Part A and Part B:

For this part, the lock allows a certain number (n) of incorrect attempts. The number of times an invalid key value can be input ranges from 0 to 7 and should be set via a combination of three separate inputs: X1, X2 and X3 Note: You can combine the 3 inputs into a single 3 bit input. With an n value of 0 you can make 0 incorrect key attempts (ie. The first attempt has to work and the OPEN LED has to light up and be set to 1).

Using the same circuit as Part A, add additional circuitry to count how many incorrect attempts have been made.

Counting incorrect key attempts (for the case where n is greater than 0): If the number of incorrect attempts in a row is equal to n (the total number of allowable incorrect attempts) then the lock is permanently locked and can no longer be unlocked even if the correct key value is supplied after that.

Counting incorrect key attempts (for the case where n is equal to 0) With an n value of 0 you can make 0 incorrect key attempts (ie. The first attempt has to work and the OPEN LED has to light up and be set to 1).

Reset when correctly unlocked

If the lock is unlocked before n incorrect attempts have occurred, then the count of the number of incorrect attempts resets to 0. This means that if the lock is unlocked, then n incorrect attempts will again be possible before the lock is locked forever.

The circuit will have a single LED output labelled OPEN. If, and only if, the key and lock match then the OPEN LED will be set to 1. If the key and lock value do not match the OPEN LED will be 0. If n incorrect unlocking attempts are made, the OPEN LED will remain at 0 and cannot be set to 1.

Values for X1, X2, X3

For Part B only, you may use only the three basic logic gates (AND, OR, NOT) with maximum 2 inputs, as well as the more advanced counter and comparator circuits (only those two) from the Logisim circuit library.