Q1. By using a neat flow chart describe the operations comprised in an interrupt cycle.

Q2. There are four resisters A, B, C & D. Design a common bus data path with required logic circuit to perform the transfer of content of any register to self or any other registers. Draw the logic circuit efficiently.

Q3. A computer Employs RAM chips of 2568 and ROM chips of 10248. The computer system requires 2k bytes of RAM, 4k bytes of ROM and four interface units, each by four registers. A memory mapped I/O configuration is employed. The two highest order bits of the address bus are assigned 00 for RAM, 01 for ROM and 10 for the interface registers.

a) Find out the number of RAM & ROM chips which are required?
b) Draw a memory address map for the system.
c) prepare down the address range in hexadecimal for RAM, ROM and interface.

Q4. What do you mean by cache memory? Describe the various mappings used in the cache organization with their merits and demerits.

Q5. A virtual memory system consists of an address space of 8k words, a memory space of 4k words, and page and block size of 1k words. The given page reference changes take place throughout a given time interval. Find out four pages which are resident in main memory after each page reference change if the replacement algorithm employed is:

a) FIFO
b) LRU.

Page reference order: 4, 2, 0, 1, 2, 6, 1, 4, 0, 1, 0, 2, 3, 5, 7.

Q6. Describe Daisy-chaining priority to handle the interrupts in detail with the help of a diagram.