You are required to design a simple CMOS circuit comprising of a two-input NOR gate. You are required to demonstrate the layout (plan view) of circuit, after computing the aspect ratio (W/L) of the transistor. The layout of the circuit must include the vDD and ground lines.
VDD = 3V, VT = 0.3V, C0 = 3x10-4 Fm-2, electron mobility = 0.1m2V-1s-1, hole mobility = 0.05m2V-1s1 minimum feature size = 0.3µm, maximum alignment error = 0.3µm.
The area of the circuit must be a minimum.
Understanding alignment and minimum feature size:
• The minimum feature size is the smallest dimension which can be defined on a chip. This will often be the channel length L.
• The various layers have to be aligned (registered) with each other. This involves some inaccuracy in placing any mask relative to the pattern already on silicon. It is essential to know how large (in microns) the error can be. You should allow for this in the design.
Make sure to include LEGEND (what is poly-, metal, n-well, n+ diffusion, p+ diffusion etc.) + SCALE (either µm or using λ-rule).