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problem 1) prepare down VHDL code for binary to 7 segment display.

problem 3) prepare a counter model with the clock input clk of type bit, and an output q of type integer. Behavioral architecture body must contain a process which declares a count variable initialized to zero. Process must wait for changes on clk. When clk changes to ‘1’ the process must increment the count and assign its value to the output port.

problem 4) Make the “clk1” and “clk2” waveforms for following two process statements. Both “clk1” and “clk2” are signals for the type bit.

P1: Process is Begin
Clk1 <=”1” after 5 ns, “0” after 10 ns;
Wait for 10ns;
End;
P2: Process is
Clk2<=’1’ after 5 ns;
Clk2<=’0’ after 10 ns;
Wait for 10ns;
End;

problem 5) Design a behavioural model of a RAM with generic constants governing the read access time, minimum prepare time, the address port and the data port width.

problem 6) describe the 8-bit serial to parallel and parallel to serial shift register and prepare code for the same.

problem 7) prepare brief notes on:

(a) Guarded signals with the help of exs.

(b) FPGA Vs. CPLD designing.

Electrical & Electronics, Engineering

• Category:- Electrical & Electronics
• Reference No.:- M98538

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