1) Specify the data types specified in VHDL.
2) describe the term delta delay?
3) prepare down the syntax for the wait statement.
4) describe what is component instantiation? Provide an ex.
5) describe what is meant by the guarded signals?
6) describe the need for the configuration?
7) describe what is meant by the package? Provide an ex.
8) Specify the design units in the Library file.
9) describe what is meant by an identifier?
10) prepare down few conditional statements in the verilog HDL.