Problem 1.
Consider that the meaning of the BUN instruction of the Basic Computer is changed to implement the relative addressing mode, i.e PC <- PC + AR instead of PC<- AR.
a) Prepare an optimal operation sequence to implement the new version, but make sure that the value of AC is not changed at the end of your implementation.
b) Is it possible to prepare an operation sequence to implement the new version such that, at the end of the implementation, the values DR and AC are unchanged? If yes, write such an optimal sequence. Otherwise justify why it is not possible.
Problem 2.
Write an optimal sequence of control microinstruction to implement the subsequent register transfer:
x: AR<- AR +DR, DR <- DR + 1
Your solution could use the minimum number of cycles and it should leave AC unchanged: You can consider that AC contains an 11-bit quantity.
Problem 3.
Archie Tecture has to write Computer code that contains lots of "spinning loops" of the form:
Loop: ISZ A
BUN loop
Other code....
He believes that all his "spinning loops" will run faster if he implements them once he makes the subsequent changes to the basic computer.
-Add a register to the bus system CTR(count register) to be selected with S1=0
-Replace the ISZ instruction with an instruction that loads a value into CTR:
LDC Address CTR<- M[Address]
- Add a register reference instruction ICSZ with the semantics: Increment CTR and skip next instruction if zero.
a) Using as a model table 5-6, write the register transfer statements for the new instruction ICSZ and LDC
b)Is Archie correct assuming that all his "spinning loops" will run faster once he reimplements them using the next instruction? Justify carefully your answer.
Problem 4.
Most machines have a shift left unit attached to the ALU. Using 4x1 multiplexors and D-flip-flops, Prepare a 4-bit shifter that accommodates these four operations: no shift, Circular shift left, Circular shift right, logical shift right. The most significant bit is the sign bit.