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1) Draw a 4-bit carry look ahead adder and prepare down the verilog HDL for it.

2) Draw 4X1 multiplexer and prepare down the HDL for it in all four modelling:

3) Briefly describe behavioral modelling (all functions) with suitable ex:

4) Sketch and develop a project in HDL to compare x5x4x3x2x1x0 with y5y4y3y2y1y0. Test the output by means of test bench.

5) Describe the following with suitable ex:

i) Tasks and functions

ii) Test bench for multiplexer

iii) prepare down difference between always and initial.

iv) Blocking and non-blocking statements

6) prepare down the two blocks in behavioural modelling.

7) What do you mean by FSM?

8) What do you understand by Data flow model?

9) What do you mean by Switch-level modeling?

10) Describe vector in verilog in detail.

11) prepare down the different types of modeling Verilog?

Electrical & Electronics, Engineering

  • Category:- Electrical & Electronics
  • Reference No.:- M911284

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