Two-Signal-Triggered One-Shot Circuit Figure 5.17 shows an illustrative timing diagram for a one-shot circuit that is not triggered by a single signal but rather by a pair of signals. The triggering condition is the following: the one-shot pulse (in y) must be generated if the control signal x lasts at least as long as the dv pulse (this is obviously checked only at positive clock transitions). Note in the figure that only the first pulse of x fulfills this requirement, so the one-clock-period pulse in y has to be produced only in that case. Draw the state transition diagram for a state machine capable of implementing this circuit.
