Traffic Light Controller Solve exercise 9.8 using SystemVerilog instead of VHDL.
Exercise 8 in Chapter 9
Traffic Light Controller This exercise concerns the traffic light controller of figure 8.20c.
(a) Which of the two timer control strategies (#1, section 8.5.2, or #2, section 8.5.3), if any, can be adopted to implement this FSM?
(b) Implement it using VHDL. Check whether the number of DFFs inferred by the compiler matches the prediction made in section 8.11.5 for each encoding option (sequential, Gray, Johnson, and one-hot). Recall that the predictions must be adjusted in case the clock frequency is different from 50 MHz.
(c) Physically test your design in the FPGA development board. Use three switches to produce stby, test, and rst, and six LEDs to display the outputs.
(d) At this point add the following feature (modify the design and download it to the FPGA board): the yellow lights should blink (at 0.5 Hz) while the circuit is in the standby mode.
