This problem involves the design of a parallel adder-subtracter for 8-bit numbers expressed in sign and magnitude notation. The inputs X and Y are in sign and magnitude, and the output Z must be in sign and magnitude. Internal computation may be done in either 2's complement or 1's complement (specify which you use), but no credit will be given if you assume the inputs X and Y are in 1's or 2's complement. If the input signal Sub = 1, then Z = X - Y, else Z = X + Y. Your circuit must work for all combinations of positive and negative inputs for both add and subtract. You may use only the following components: an 8-bit adder, a 1's complementer (for the input Y), a second complementer (which may be either 1's complement or 2's complement-specify which you use), and a combinational logic circuit to generate control signals. (Hint: -X + Y =- (X - Y). Also generate an overflow signal that is 1 if the result cannot be represented in 8-bit sign and magnitude.)

(a) Draw the block diagram. No registers, multiplexers, or tristate busses are allowed.

(b) Give a truth table for the logic circuit that generates the necessary control signals. Inputs for the table should be Sub, Xs, and Ys in that order, where Xs is the sign of X and Ys is the sign of Y.

(c) Explain how you would determine the overflow and give an appropriate equation.