Suppose a clocked synchronous system uses registers with setup time of 150ps and clock-to-output delay of 400ps. Three register-toregister paths in the datapath have propagation delays of 600ps, 900ps and 1.3ns, respectively.
a) What is the maximum clock frequency at which the datapath can be operated?
b) If the path with a delay of 1.3ns is optimized to reduce its delay to 800ps, what is the maximum clock frequency for the optimized datapath?