Reference-Value Definer with LCD Display

(a) Solve exercise 8.11 if not done yet. The reference values should be {000, 005, 010, 050, 100, 200, 400, 800}.

(b) Draw the state transition diagram for a second circuit, which should implement an LCD driver to have the reference value displayed on an alphanumeric LCD.

(c) Implement the complete circuit using VHDL or SystemVerilog and test it in the FPGA development board.

Exercise 11 in Chapter 8

Arbitrary Reference-Value Definer with Up/Down Controls Figure 8.19b shows an alternative for implementing a reference-value definer with up and down controls, which is advantageous when the reference values are few and irregular (arbitrary). The first block was already treated in the previous exercise. Draw a state transition diagram for an FSM capable of implementing the second block, with eight reference values ( r1, r2, ... , r8). Recall that the inputs to this machine can only be x1x2 = " 00 "( idle), " 10 "( up), or " 01 "( down), with any nonzero input lasting only one clock period (as determined by the previous block).