Project 1: Input XOR

Introduction:

This project consists of the getting familiar with Cadence VLSI design. Implementing a 3 input XOR circuit, by creating the schematic, layout, and comparing the layout versus the schematic. Also, familiarize ourselves with the design rules by applying a design rule check to the layout and schematic. Finally, we will simulate the design to see if the 3 input XOR is properly working to what we know.

Analysis:

** The file being used for the final project is called XOR_3. This is the file that was used for the simulation, DRC, extraction, and LVS.

Part A: Enter the Schematic of the CMOS Cell.

Part B: Simulate the cell using SPICE from within Cadence starting from the extracted schematic.

Part C: Make a layout of the cell. Include wells and well contact, labels, etc.

Part D: Perform LVS to verify that the schematic and layout match perfectly. You must check transistor sizes as well as mere connectivity.

Part E: Perform DRC to check that you have not violated any layout design rules.

Part F: Simulate the circuit again, starting from the extracted layout, noting any differences.

Project 2.

The primary goal of this project is for you to develop skills in expert circuit design (including the use of cells), simulation and layout. You may work individually or in groups of 2.

Your task is to implement a fast 16-­-bit CMOS adder. You can implement any kind of adder EXCEPT for a standard static ripple adder. So, for example, you can implement a carry-­-skip or carry look-­-ahead adder, Laner-­-Fischer, Brent-­-Kung, Kogge-­-Stone, Slanskly, Han-­-Carlson, etc. You CAN do a ripple adder as long as you do it in an alternative logic family such as Domino logic or pass-­-transistor logic (hint: one of these is likely to be easiest and perhaps smallest, whereas something like Han-­- Carleson, etc., will likely be fastest).

To add an element of fun, awards may be given to the student teams that produce the fastest adders and the smallest ones, with double-­-points for both! Professor Kleinfelder reserves the right to choose the winner(s) based on his judgment of the over-­-all quality of the projects and not merely on performance numbers.

To give the contest a level playing field, all inputs must be designed to be compatible with minimum-­-sized input inverters or buffers as input signals. Although you need not include these, no excessively large transistors should be used at the inputs (you can, if you wish, use extra inverters, but include them in your area computation).

Both the inputs and the outputs must all be non-­-inverting. If you require A an A_bar, etc., as inputs, then you must include the extra inverters to produce them. The exception is for fully-­-differential designs, which may use both in and in_bar for all inputs and outputs without adding special inverters to provide them.

Of course, it must function correctly as an adder! It is also your job to determine the critical path for your adder. In many cases - but not always -­- it would be something like this: Initially have all inputs (A0-­-15, B0-­-15, Cin) low, and then raise all A's and Cin high simultaneously. Measure the time between when Cin goes high and Cout goes high, and the time until the slowest Sum bit changes. After it settles, make all inputs low again and measure those delays too. Do it yet again, but with all B's going high, and then going low. The speed of the chip is the WORST (longest) delay time for any of these transitions.

To measure the size of your adder, you will calculate the area in square microns of the smallest rectangle (on an X-­-Y grid, not tilted) that will encompass the entire adder along with any necessary inverters.

To measure both, multiply area times the worst-­-case rise/fall time. (Smaller is better, obviously.)

Creativity is encouraged, and I'm looking forward to seeing how people try to go as fast as possible. Gaming the adder such that it will only work fast for the above test is not fair, though. On the other hand, I will respect efforts to make the smallest possible adder regardless of speed.

Your professional-­-looking report should include the following:

- A description of the adder's approach and other commentary, conclusions, etc. You may use figures from the book with appropriate attribution, but you may NOT use figures, text, etc. from the internet, other student's work etc. Copyright is violated by over-­-use of others' figures, etc., even with attribution.

- Plots and schematics of the whole adder and the various cells (1 bit adder, etc.). Please provide a separate plot that shows the cell hierarchy.

- You MUST use cells appropriately. For example, people would normally have a cell for one bit, for groups of bits (e.g. every 4), for any ancillary logic, and for the whole adder. Use a minimum of "painted" connections (metal, etc., painted over or between the cells).

Ideally, cells should abut without any painted connections between them. Designs that are "flat" - without hierarchy - will be considered seriously incomplete.

- Simulation results that demonstrates speed, e.g., shows the propagation of the carry down the whole chain and the evolution of the sum bits. Please provide simulation results from the extracted layout.

- A summary box giving the size and worst-­-case speed of the adder, plus the two results multiplied together.

Example of an adder :

http://cmosedu.com/jbaker/courses/ee421L/f14/students/delatorr/lab%206/lab6.html