Programmable logic design Assignment

Problem -

Design the instruction set architecture of a single cycle processor with 18 bit wide instructions, and data-word width of your choice. Show the hardware implementation details of the processor. In particular, provide the

-Instruction set along with the binary codes

-Instruction encoding/decoding logic

-Discuss various tradeoffs made in your design to optimize the following:

• Instruction coverage
• Dataword width,
• Number of registers,
• Memory addressing scheme (byte or word addressable, base/offset based addressing)
• Memory addresses and offset range
• Jump offset range
• Branch offset range

-Show the data path needed to implement your design

-Discuss the control signals and their logic.

Notes.

The complexity and the effort needed depend significantly on the data word width of the processor. This mark automatically depends on the data word width. You should aim for at least 16 bit wide data words.

The utility and efficiency of a processor depends significantly on the number of registers. Hence one prefers to have as many resgisters as possible. However, having more than 32 registers typically slows down a processor due to the increase in the address decoding time.

Similarly, it is desirable to have large memory offset range, jump offset range and branch offset range.

Aim to implement as many instructions from the standard MIPS instruction set as possible, and justify why it is not required/possible to implement more.

Attachment:- Assignment.rar