Problem: The purpose of this problem is to design two circuits: a serial odd parity generator and a serial odd parity checker.
1. Serial Parity Generator
The generator has two inputs:
• D - The bit that is being transmitted this clock cycle.
• rst - reset the generator. Asserting this input makes the parity generator assume that no 1's have ever been transmitted. This input must be effective even from invalid states.
And one output:
• P- The odd parity bit for all data received since the circuit was reset. This output should be 0 the clock cycle after a reset since no zeroes or ones have been received by the circuit at that point.
Once reset, the generator tracks the number of l's being transmitted. This parity generator can be used to generate odd parity for a data sequence of any length. To generate parity for a 3 bit data value takes 5 clock cycles (reset for one clock cycle, 3 data transmitted, 1 cycle with a valid parity value).
a. Design a finite state machine (FSM) for this device. Use the fewest number of states possible.
b. Write a truth table for the next state and output logic. Use don't cares for output or next state values of any undefined states. Specify state bit mappings using a minimum bit width binary encoding using the lowest possible numbers for the encodings (i.e. any unused states would have the highest binary values. The initial state must have an encoding equivalent to the decimal value zero, Use K-maps to derive optimized logic equations for the next state bits and logic outputs from the truth table.
c. Draw the circuit for the parity generator based on the equations from part c using flip flops that do not have built-in reset capabilities.
2. Parity Checker
The receiver has two inputs:
• S - Start the checker. This only needs to be high for one clock cycle to start the parity checker. It must be set high the same clock cycle that the first data bit is received.
• R - The bit that was received this clock cycle.
And two outputs:
• G - Parity check is passed (good). After all bits have been received (i.e. the fifth clock cycle), this bit is set to I if no error was detected. It is set to '0' otherwise.
Before being started, the FSM sits in a wait state. When started, the checker will receive a sequence of 4 bits; one per clock cycle. The first 3 bits are the transmitted data. The fourth bit is an odd parity bit. The checker must determine if the parity is correct (i.e. is the total number of I 's in the data sequence odd) and set an error bit if it is not. Once the sequence has been checked, the checker waits for the start bit to be set again to check another sequence.