Part -1:

Question 1 (a) A high pass filter has the following specification:

fp = 8kHz    Lp = 0.5dB
fs = 6.8kHz  Ls = 26dB

Design a Chebyshev passive filter (R₁=R_L=1k?) that meets the specification using the filter prototype design table given at the end of the paper. In your design, you must show the following:

(i) The required order of a Chebyshev filter that meets the above specifications

(ii) The prototype circuit, prototype component values, actual circuit and filter actual component values

(b) Figure Q1 (b) shows a 2nd order passive filter. Giving:

R=2kΩ
C=0.5uF

(i) Determine the transfer function of the filter in Figure Q1(b).

(ii) At which frequency the magnitude response of the filter is maximal.

(iii) What is the filter's gain at DC, 1/2ΠRC and f = 100.1/2ΠRC

(c) (i) List the followings:

Magnitude response of the Nth-order low pass Butterworth filter transfer function;

Magnitude response the of the Nth-order low pass Chebyshev filter transfer function.

(ii) Sketch the magnitude response for each of the filters in Q1(c)(i) and using approximation to show that Chebyshev filter has a constant higher attenuation than its Butterworth counterpart of the same order in stop band (saying 0.2ω > ω_p or higher).

(iii) Calculate the value of attenuation obtained at a frequency 1.6 times the 3-dB frequency of a 7th-order Butterworth filter, and compare it to the first order filter

Question 2:

A phase locked loop shown in Figure Q2 has a centre frequency of f_c =100kHz, voltage controlled oscillator gain k_o=45kHz/v and phase detector gain kd=1.5rad/v.

There is no other gain in the loop, and the loop filter is F(s ) = 1. The phase locked loop is used to demodulate an FSK data stream where logic 0s are keyed as f0=95kHz, and logic 1s are keyed as f₁=105kHz . The bit duration is Tb=100uS.

(a) Determine the transfer function H( s)= θ₂(s )/θ₁(s ) of the loop.

(b) Determine the rise time of the VCO control voltage in response to a step change in frequency

(c) Determine the control transfer function V_d(s)/ω₁(s ) of the loop and hence phase detector output V_d(t) when the input changes from 95 kHz to 105 kHz.

Part -2: Digital Systems

- All your Model and Test Bench VHDL source files. The code should be properly commented.
- Report (1200 words) which should record:

1. At System Level:
- Block diagram showing the structure of the system with all its sub-blocks and their interconnections.
- The "ports" interface (inputs and outputs of an entity, process sensitivity list) of each sub-block
- Description of the integration of the sub-systems into the top level.

2. For each Sub-System:
- Summary of its functionality requirements
- Description with justification of its design. The VHDL constructs used to code the design should be identified and argued with reference to the relevant lines of code.

3. For each Test Bench:
- Brief description of the test vectors used
- Annotated simulation waveforms highlighting sections where your modelling to the system is correct / incorrect