Manchester encoding can be used to transmit a stream of bits over a single data wire, with no auxiliary clock information. Each bit is represented by one of the following patterns, where T is the period of the clock used to encode the signal. Note that a Manchester-encoded signal always changes value in the middle of ach bit cell.

A block diagram of a Manchester decoder is shown below. The decoder is a clocked sequential machine whose state memory consists of just two edge-triggered D flip-flops.

The combinational portion of the decoder has as inputs the Manchester-encoded signal and the current state of the two flip-flops. The combinational logic outputs the next state N₁ and N₀ for the two flip-flops and the clock signal C generated for the stream of serial data. The truth table of the combinational logic is as follows:

Note that the serial data out from the decoder is just a copy of the Manchesterencoded data in. Thus the decoder must place positive transitions in its clock output C timed to correspond to the correct logic values already present in the Manchester-encoded stream. The positive-going edge of each clock pulse must occur while the Manchester-encode data has the proper value for the serial output; but there is no particular restriction that the clock output must return to zero before the Manchester-encoded input changes value, or that all output clock pulses be of the same duration or evenly spaced in time. The sample timing diagram below shows an original stream of serial input data and its clock, the. result of Manchester en coding that stream, and a clock output waveform that meets the conditions stated. (This is not intended to imply that the specific "clock out" signal shown would actually be generated by the above circuit.)

The period of the "decoder clock" that drives the D flip-flops need not be T; in general, it will be faster.

A. When the decoder is properly "in synchronization" with the Manchester-encoded input data, it will be either in state 10 or in state 11 when the data make the transition in the middle of a bit cell. The decoder will enter state 00 (causing a positive transition on the clock output C) at the next decoder-clock pulse. Assuming that the decoder starts out in synchronization, what is the longest decoder-clock period for which the decoder is guaranteed to operate correctly? (State your answer as a fraction of T.)

B. What is the shortest decoder-clock period for which the decoder is guaranteed to operate correctly? (State your answer as a fraction of T.) Again, assume that the decoder starts out in synchronization.

C. Assume that the decoder-clock period is within the valid range you identified above. Give an input signal that will get the decoder in synchronization within a time 2T, no matter what state the decoder is in initially. Don worry about what pulses are output on the clock output C during this synchronization process.

D. Describe a scenario that might result in your circuit being driven into a metastable state.