Laboratory: AC Power Analysis & Fourier Analysis

Question 1 - Analytical Section

Show that for any periodic signal of period T₀, the Fourier transform is equal to the Fourier series coefficients at the harmonics (integer multiples) of the fundamental frequency ω₀ = 2π/T₀ and zero at all other frequencies.

Question 2 - Analytical and Simulation Section

A. Determine an expression for the frequency response of following system shown below in Figure 1.

B. Choose values of R₁, L₁ and C₁, such that the magnitude response of the system is at least 1/√2 between 80kHz and 120kHz and as low as possible at all other frequencies, by simulation.

C. Sketch its magnitude response, clearly indicating the magnitude and frequency of key points in the response, including the half-power points.

Question 3 - Analytical Section

A signal, x(t), is given as below:

x(t) = _n=-∞∑^∞ 1/T₀(t - nT₀)(-1)ⁿ[u(t - nT₀) - u(t - (n + 1)T₀)]

A. Sketch x(t).

B. Sketch x(2t - T₀)

C. Represent x(t) as a complex exponential Fourier series.

Question 4 - Analytical Section

In the circuit below, ω is adjusted at the source so that the power factor pf = 1. Find Q_coil, Q_circuit and v(t)

Question 5 - Analytical Section

(a) Show that if R_L = R_C = √(L/C), then the power factor seen by the source in the circuit shown below is unity for all ω.

(b) If L = 12mH, C = 3nF, R = 3kΩ, R_L = R_C = √(L/C) and i(t) = 5cos1000t mA, find the impedance Z seen by the source as well as v(t).

Question 6 - Analytical Section

In the circuit shown below, find the maximum average power that can be transferred to Z_L as well as Z_L itself.

SAMPLE EXAM -

1. Simulation Task

The following combinational logic design has 3 inputs and 2 outputs. Create the design and simulate it to fill out the truth table. DO NOT generate the truth table by hand. You will need to show the maker:

(i) Schematic or Verilog HDL code of the circuit

(ii) The Verilog test fixture (Test Bench)

(iii) Simulation output

2. Implementation Task

Create a binary to hexadecimal converter. Use SW3-0 as the input and the left most 7 segment display ONLY as the output. SW3-0 should be interpreted as a 4bit unsigned binary number with SW3 as the MSB. The 7 segment should display 0-F based on the input number, both upper and lower case may be used. You need to show to the marker:

(i) Schematic or Verilog HDL code of the circuit

(ii) Constraint file

(iii) Demonstrate the working implementation

Create a digital debounce. The debounce is timing based, and should only acknowledge pulses greater than a set period. To make it easier to demonstrate in this lab, set the period to 1s. The input should be BTN 0, output should be LED 0. LED0 should only turn on if BTN 0 has be high for 1s and should not turn o unless BTN 0 has been released for more than 1s.

You will need to show the maker:

(i) Schematic or Verilog HDL code of the circuit

(ii) Constraint file

(iii) Demonstrate the working implementation.