In Example 9.6, we mentioned that we could reduce the memory bandwidth consumed by the Sobel accelerator by storing rows of pixels in small memories, so that each pixel need only be read from memory once. Revise Figure 9.6 to show how this might be done using two row memories. Hint: It may simplify your design to assume that a memory can read and modify a location in a single cycle, with the read data provided on the data output and the new data taken from the data input. Memory components in some implementation fabrics can operate in this way.
Example 9.6
Suppose the memory in which the original and derivative images are stored is 32 bits wide, and that each 8-bit byte is individually addressed. Video frames are stored with one byte per pixel. The pixels of a row in a frame are stored from left to right at successive addresses, and rows are stored top to bottom, one after another in memory. Each memory read or write access takes 20ns, consisting of two cycles of a 100MHz system clock. Can the memory access data fast enough?
