1) Describe Sequential and Concurrent assignments with an ex in detail.

2) Illustrate the following terms:

a) Transport delay

b) Delta delay

c) Inertial delay.

3) describe the Wait statement with appropriate ex.

4) describe the component declaration and Component instantiation in detail.

5) Describe about the Subprogram overloading and Operator over loading in detail.

6) describe the guarded Signals with an appropriate ex.

7) Describe the modelling synchronous logic with an appropriate ex.

8) Describe the Modelling Moore FSM by giving the suitable ex.

9) describe the Verilog Structural modeling by giving the suitable ex.

10) Describe the Operands and Operators in Verilog in detail.