Do the following calculations for the circuit represented by the schematic for our EE3722 PCB design lab. Assume that the output of the counter bits is 4.95 volts and that the 1% resistors have a maximum variation of +/- 2%. Except for Question 3, assume that the 50 kΩ potentiometer has been adjusted so that the op amp output waveform is symmetrically centered around zero volts. Report your results to five significant figures.

1. (a) Calculate the nominal ± output voltage range (e.g., if the output voltage range corresponding to the 0000 through 1111 (0 - F hex) count of the four-bit counter is 20 volts, then the ±range would be ±10 volts). Calculate the (b) minimum and (c) maximum output voltage ranges based on variation of the resistors.

2. Calculate the maximum nominal current in the 49.9 kΩ feedback resistor when the count is 1111. This count will correspond with the minimum output voltage of ∼ -10 volts, the assumed symmetrical output voltage range centered around zero volts.

3. Calculate the nominal offset voltage range (when the pot. Is adjusted over its full range). This is independent of the effects of the output due to the counter.

4. Calculate the smallest nominal output voltage step (use nominal values of the resistors).

5. Using the actual nominal resistor values, calculate the smallest and largest current demand from a counter output bit. Counter bit Q₀ will supply the smallest current and counter bit Q₃ will supply the largest current.

Attachment:- Assignment.rar