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Develop a Verilog model of the sequential multiplier in Exercise 4.20, including both the datapath and the control section.

Exercise 4.20

Identify the control steps required for sequential multiplication using the datapath described in Example 4.4, and develop a finite-state machine for the control section. Assume that the x and y operand values are valid on a cycle when a control signal, start, is 1. Generate a control signal, done, that is 1 when when the multiplication is complete. Use a 4-bit counter to count the successive accumulation steps.

Example 4.4

In Chapter 3, we showed how to perform multiplication of unsigned integers by addition of partial products. Construct a multiplier for two 16-bit operands containing just one adder that adds successive partial products over successive clock cycles. The fi nal product is 32 bits.

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