1) prepare down the design procedure for 8 bit carry look ahead adder.
2) Design CMOS implementation of 4-to-1 MUX by using transmission gates.
3) Design the basic physical design for the inverter AND, OR and half-adder.
4) Design in detail about manufacturing of test principles.
5) Draw a circuit for finding the 9's compliment of a BCD number by using 4-bit binary adder and some external logic gates
6) What do you mean by physical verification?
7) prepare down the levels at which testing of a chip can be done.
8) prepare down the approaches in design for testability.
9) What is called as boundary scan register?
10) Draw a set of CMOS gates to execute the sum function.
11) Describe concept of clock distribution and power distribution in detail.