Design and simulate a CMOS current mirror to meet certain criteria for output resistance, minimum output voltage, size and power consumption.
Technology: AMI 0.6u 5V CMOS
Power supply: Vdd = 5 V
The nominal ratio of IOUT to IREF is equal to 1.00±0.01 over the range 1uA ≤ IIN ≤ 100uA
The quiescent DC power dissipation should be less than 0.5mW with VDD = 5V, IOUT = IIN = 50uA
TOX = 1.41E-8 m
U0 = 533.6953445 cm2
VTH0 = 0.7086 V
TOX = 1.41E-8 m
U0 = 202.4540953 cm2
VTH0 = -0.9179952V
k’ = UO ⋅ COX , COX = εOX / TOX, εOX = 3.5E-13 F/cm
Project Report Guidelines:
The report should be comprehensive, clear and brief. The report must be typed. Maximum pages: 10 pages (11 point or larger font, 1 & 1/2 line spacing or larger).
Here is an outline of what the report should contain with maximum page limits:
1) A short introduction of the design problem and a statement of the design goals.
2) Show how you approached the design specifications and how you find outd the MOSFET widths and lengths. Discuss your design insights and tradeoffs in sizing the transistors.
3) A circuit schematic showing all MOSFET widths and lengths and SPICE node numbers.
4) A table of all pertinent find outd and simulated results. Whenever possible, the simulated values should be compared to the find outd values and percentage errors given.
5) Discussion of your results and conclusions about the design. Discuss and describe the differences between your find outd and simulated results. If you failed to meet one or more of the design criteria, describe why. Suggest how your design could be further improved. Comment on any other aspects of the design as you see fit.