Design and simulate a 32-bit MIPS ALU using VHDL with overflow and zero detect. The
ALU should implement 10 R-type operations.

Your VHDL description should be structural and constructed from 3 behavioral VHDL 1-bit ALU blocks, a special behavioral VHDL 1-bit ALU block for the most significant bit and a behavioral VHDL block for the zero detect logic. Note: In your 4-bit ALU, the carry-out is generated through Carry Look-ahead logic, not through ripple carry logic. So you need to implement a behavioral VHDL logic for the Carry Look-ahead.
The next step is to construct the 32-bit ALU by wiring EIGHT 4-bit ALU blocks. The final overflow output of the 32-bit ALU is the overflow output from the most significant 4-bit ALU block. You also need a behavioral VHDL block for generating the final zero detection output. Note: For the 32-bit ALU, you need to implement Hierarchical Carry Lookahead: the overall carry out using signals provided by the 4-bit ALU's carry lookahead logic. We still use carry look-ahead to generate the 32 bit ALU's carry out( not a A Partial Carry Lookahead Adder).

Your behavioral blocks should be constructed from CSA's only using the following "gate library":
inverters (1 ns delay)
2-input NANDs (2 ns delay)
3-input NANDs (3 ns delay)2-input NORs (2 ns delay)
3-input NORs (3 ns delay)
2-input XORs (3 ns delay)