design a digital lock. The lock will have four buttons for you to enter a secret three-digit code to unlock it. You will use the pushbuttons RON(3:0) on the FPGA board for this - RON(0) will represent the digit ‘0', RON(1) the digit ‘1', RON(2) the digit ‘2', and RON(3) the digit ‘3'. The secret code is 1-0-3. So you must press ‘1', followed by ‘0', and then ‘3' in order to open the lock. If you entered the correct code, LED LD0 will light up to indicate that the lock is open. If the code is incorrect, LD7 will light up instead. You must make three button pressings before you know if you have entered the correct code or not. While you are keying in the code, all LEDs will be off.
The following is the top-level schematic of the digital lock. It consists of 2 modules - the lock module and the pushbutton debouncing module. The ‘CLR' input is active low and is mapped to a slide switch. The ‘clock' is to be connected to the onboard 50Mhz FPGA clock at location B8. Z(0) is mapped to LD0 to indicate a correct code while z(1) is mapped to LD7 to indicate an incorrect code.