design a circuit which accepts 2-bits input DUTY (‘01' for 12.5%, ‘10' for 25% and ‘11' for 37.5%). Assume 0% duty (all low) for input DUTY='00'. The circuit will need to be sequential and sensitive to a positive edge of another input CLK. Use the function generator or a de-bounced push button to provide CLK. Use another push button for the reset input RST. Connect the PWM output to an LED, for preliminary testing with slow clock frequency, then to the oscilloscope to show final results with multiple frequencies between 10 KHz to 1MHz. In the final demonstration, connect CLK to CH1, and PWM to CH2, and show both on the same screen of the oscilloscope. Attach sketches or images of the results in the report.