1) Deduce the expression for drain current of the mos transistor in cut of, saturation and non-saturation region.
2) Describe about the dynamic behavior of CMOS inverter.
3) Describe the working of the domino logic with essential diagrams.
4) Describe the working of np-CMOS logic with required diagrams.
5) Describe the working of C2MOS register with neat diagram.
6) describe about the Baugh –Wooley multiplier structure in brief.
7) Describe the physical design flow with proper sketch.
8) Illustrate how the network can be partitioned by using the Kernighan lin algorithm with suitable ex.
9) Describe the floor planning tools in the floor planning a cell based ASIC with suitable diagram.
10) Describe the I/O and power planning.