Q1. Design a 2-to-1 multiplexer and XOR gate by using the transmission gates.
Q2. Design a Resistive Load Complex gate and CMOS Complex gate for the given expression:
[Z = A(D + E) + BC]‾
Q3. Draw a schematic of the 6T SRAM cell and describe its Read and prepare operations.
Q4. List and describe the Standard VHDL data types and Extended VHDL data types. As well describe the difference between the data flow model and behavioral model.
Q5. Describe the significance of scaling of MOS transistor dimensions. Describe the types of scaling and show the effects of the parameters in full scaling.