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Consider two SRAMs. One is 256K x 8 and has a tRC of 8 ns. The other is 128K x 16 and has a tRC of 10ns.
a. What are the effective bandwidths of the two devices?
b. Now, consider that the devices are to be used to provide data to a 32-bit bus. What is the data rate that can be sustained on the bus if it is driven by 4 of the 256Kx8 chips in parallel?
c.What is the corresponding bus data rate if two of the 128K x 16 SRAMs are used in parallel?
d.Ignoring control, power, and ground pins, discuss the trade-offs in pin count between a 16Mb
SRAM organized as a x8 device or as a x32 device. Assume data pins are bidirectional.
e. Assume you have an embedded system that requires a new byte of memory data every 6ns.
How might you use the 128K x 16 SRAM chip to achieve this?

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