Consider a CMOS inverter.
(a) Show that when vI ≅ VDD , the resistance of the NMOS device is approximately 1/[(W/L)n(VDD - VT N )], and when vI ≅ 0, the resistance of the PMOS device is approximately 1/[(W/L)p(VDD + VT P)].
(b) Using the results of part (a), determine the maximum current that the NMOS device can sink such that the output voltage stays below 0.5 V, and determine the maximum current that the PMOS device can source such that the output voltage does not drop more than 0.5 V below VDD.