An N-bit up/down counter is a sequential circuit with a clock input and an up/down control input. Wen control is 1, the circuit counts up, modulo 2N, on each rising edge of the clock. In other words, the present-state outputs of the circuit, interpreted as a positive binary integer, increase by 1 on each clock pulse; the next count after 2N - 1 goes back to 0. Wen the control signal is 0, the circuit decrements, or counts down, modulo 2N on each rising edge of the clock.
A. Draw a state-transition diagram for a 2-bit up/down counter. You should have one state for each of the possible output integers. Label each arc with the value of the control input that causes that transition.
B. Think of the up/down counter of part A as a clocked sequential circuit of the form given in figure 4.15. Derive the truth table for the combinational logic, giving the next-state functions, N1 and N0, as functions of the present states, S1 and S0, and the control input.
C. Draw the Karnaugh maps and give Boolean equations for the next-state functions NI and NO derived in part B.
