A semiconductor company has the following costs associated with Product X:
- Fixed cost of $1B ($1,000,000,000)
- Die cost of $6 at a die yield of 50%
- Testing and packaging cost of $3 per die
- A final test yield of 90% with a product volume of 500M (500,000,000) chips
a) What is the cost per IC (considering both fixed and variable costs)?
b) Suppose that you are a strategic planner for this company and you need to reduce the cost to make profit. Which one is a better strategy?
Strategy 1: Reduce the fixed operating cost by 10%, i.e., by $100,000,000, with a potential reduction in volume which is negligible.
Strategy 2: Spend an extra Research and Development cost of $200,000,000 to improve the die yield from 50% to 75%.
Consider a 2-input NOR gate. Is the (i) fall time and (b) rise time the same for all combinations of inputs?
As you will find out later in the class, using basic gates with many inputs is not necessarily a good idea. As such, no more than 3 inputs per gate are typically allowed in practice. Design a 6-input OR gate using basic gates with 3 inputs each. Draw the transistor-level diagram of the design.