A purely 8-bit external data bus Motorola 68000 microprocessor is used in a data acquisition system. The system has 8K Bytes of EPROM, 8K Bytes of SRAM, and an 8-bit microprocessor-compatible Analog-to-Digital Convertor(A/D). EPROM space begains at address $000000 and occupies the full 8K Bytes of EPROM space. EPROM space is immidiately followed by SRAM which spans the 8K Bytes of SRAM space. SRAM space is followed by a single 8-bit A/D. WE WILL USE PARTIAL DECODING (8K BLOCK, EACH, FOR ROM, RAM AND A/D)
The A/D is connected so that it interrupts the microprocessor via INTERRUPT level 4 using AUTOVECTOR with a vector number 28 decimal.
The system works as follows. When the main program starts to run, the microprocessor commands the A/D to convert. The microprocessor then sits in a dummy loop until the A/D interrupts, after it has completed the conversion and data is available.
The job of the interrupt subroutine is to read the converted data from A/D, move the converted data into memory, command the A/D to convert again, and return to the dummy loop in the main program n order to wait for another interrupt from the A/D.
ASSUME THAT POWER SUPPLY, CLOCK AND RESET CIRCUITS HAVE ALREADY BEEN DESIGNED. DO NOT SHOW THOSE IN YOUR DESIGNS BELOW.
A. Draw a clearly labeled memory map of the system to indicate exactly where each single individual chip (EPROM chips, SRAM chips, A/D) will sit on the map. Provide the beginning and ending addresses of all devices. YOU SHOULD USE PARTIAL (BLOCK)DECODING TO SIMPLIFY THE DECODING.
B. Provide the address decoding table for the system. USE PARTIAL DECODING.
C. Design the complete logic details for the address decoder, glue logic and DTACK. Show interconnections for the fully labeled address, data and control bus individually labeled signals from microprocessor to address decoder as well as to memory components and A/D. Show how the individual data, address, and control signals go to the memory chips and the A/D. Draw complete logic diagrams for interrupt generation and interrupt acknowledgement circuitry.
D. Write the 68000 assembly language routine that represents the initialization of the exception vector table. Let your "Main Program" begin at address $1000. Position your INITIAL STACK POINTER at the highest even address in SRAM. Let the starting address ot your interrupt subroutine be $1800.
E. Write the 68000 assembly language routine that represents the main program (the one that contains the dummy loop). Include the Main program, any needed housekeeping insructions including appropriate initializing of the processor's Status Register as needed for proper interrupt functioning.
F. Write the 6800 assembly language routine that represents the A/D's interrupt Subroutine. Show clearly the starting address of the ISR.
G. Based on this assumption, make a list ofthe very first EIGHT bus cycle (read or wrote cycles) that the processor makes when the system's POWER SUPLY (Vcc) is first turned on. For each bus cycle, indecate what hexadecimal value of data is read from or written to what numerical address in memory. For those first FOUR bus cycles, for those cases where data is read from memory, indicate where those data are loaded to.
H. Assume that each 68000's executable line of code ( ONE EXECUTABLE INSTRUCTION ) OCCUPIES TWO BYTES OF MEMORY. At the time that the microprocessor is staring to execute the first insruction in the ISR, show what Stack Frame has been built. show hexadecimal numerical values of the Stack's addresses and what numerical data form the contents of the Stack Frame.