A CMOS output driver circuit on an IC is connected to an external transmission line. The NMOS and PMOS transistors have gate oxide thickness d = 2.0 nm and channel length L = 0.25 mum. The power rail is VDO = 1.0 V. The widths wn and wp of the NMOS and PMOS, respectively, are discussed below. Assume the transistors obey the ideal MOSFET equations. For NMOS1 and PMOS1 the threshold voltages are VT= +/- 0.3 V, respectively. The effective mobilities are mun = 250 cm2/Vs and mu P = 125 cm2/Vs, respectively. The transmission line has characteristic impedance Zo = 50 ohms and is 10 cm long. The far end is terminated with resistance RL = 50 Ohms. The transmission line has capacitance per unit length C = 100 pF/m. The end of the load resistor is held not at ground but at a DC value of VDD/2 = 0.5 V. The inputs A and B to NMOS1 and PMOS1 can be controlled separately. Explain what logic level should be applied to A and B to force the output node Vout: into a "high-Z" state where the transistors neither drive nor significantly load the transmission line. The specification on the output driver is that the output voltage should be within 0.1 V of the rails when the output logic level is high or low. What is the minimum corresponding current that the driver must be able to source and sink? Assume wn = 10 mum and wp = 20mum. Calculate the maximum lDsat for NMOS1 and PMOS1 given the rails of 0 and VDO. Sketch the l-V curves 1Dn and lDP for the two transistors vs. the output voltage Vout, for the cases A = B = 0 and A = B = VDD. Show the corresponding lDsat values and the current level you found in part

(b) above. Calculate the minimum required widths of the transistors wn and wp in order to ensure that the output voltage Vout swings to within +/- 0.1 V of the power rails when the A & B are simultaneously driven to 0 or VDO- Find the required widths to +/- 10% accuracy. (To simplify the calculations, you can approximate the transistors as appropriately-valued resistors when Vout is near the power rails.)