1 write a vhdl model for a 74hc192 synchronous 4-bit updown, Ask an Expert

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1. Write a VHDL model for a 74HC192 synchronous 4-bit up/down counter. Ignore all timing data. Your code should contain a statement of the form process(DOWN, UP, CLR, LOADB)

2. Consider the following 8-bit bi-directional synchronous shift register with parallel load capability. The notation used to represent the input/output pins is explained below.

The mode control inputs work as follows:

(a) Write an entity description for this shift register.

(b) Write an architecture description of this shift register.

(c) Draw a block diagram illustrating how two of these can be connected to form a 16-bit cyclic shift register, which is controlled by signals L and R. If L = ‘1' and R = ‘0', then the 16-bit register is cycled left. If L = ‘0' and R = ‘1', the register is cycled right. If L = R = ‘1', the 16-bit register is loaded from X(15:0). If L = R = ‘0', the register is unchanged.

(d) Write an entity description for the module in part (c). (e) Write an architecture description using the module from parts (a) and (b).

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Electrical & Electronics, Engineering

Category:- Electrical & Electronics
Reference No.:- M92178075

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