1) Using the combinational circuit design procedure discussed in the notes design, simplify and draw a combinational circuit that accepts a 3-bit number and generates a 6-bit number output equal to the square of the input number. Let the inputs be X, Y, Z and the outputs be A, B, C, D, E, F. You need to show your Truth Table, K-maps, and circuit.

2) From the following functions, create the truth table, simplify with a K-Map, and then implement with two-level NAND gate circuits.

a) F₁(A,B,C,D) = A'BC + AC' + ACD + A'B'D'

b) F₄(A,B,C,D) =                A'B + A + C' + D'

3) A combinational circuit is specified by the following three Boolean functions:

F1(a,b,c) = ∑(3,5,6)

F2(a,b,c) = ∑(1,4)

F3(a,b,c) = ∑(2,3,5,6,7)

Implement the circuit with a decoder (use block diagram for the decoder ... that is, you do not need to show the internal circuitry of the decoder)

4) Design and implement a combinational circuit with 3 inputs (a,b,c) and five outputs (A,B,C,D,E) where the outputs form a binary number representing the Fibbonacci number of the input binary number. The Fibbonnaci numbers are defined as follows:

Fib(0) = 1

Fib(1) = 1

Fib(2) = 2

Fib(n) = Fib(n-1) + Fib(n-2) where n >= 2

For example if the input abc = 101, then the output would be Fib(5) = 8 or ABCDE = 01000.

(a) Implement this with AND/OR/NOT gates. Show the Truth Table, K-maps, and circuit.

(b) Implement this with a decoder. Show the circuit.

5) Using a multiplexor, implement the function F(a,b,c,d) = ∑(0,2,4,6,8,10,11,14) assuming we connect:

a) a, b and c to the selector lines (S₂, S₁, S₀ respectively)

b) b, c and d to the selector lines (S₂, S₁, S₀ respectively)

c) a, b and d to the selector lines (S₂, S₁, S₀ respectively)