1. The MOSFET circuit in the figure below is used to perform a DC Sweep analysis of the transistor. Given the results shown, determine the effective reverse saturation current for this transistor in its diode mode of operation.
2. The DC bias circuit in the figure below uses a PMOS transistor with the parameters as indicated. What operating region will apply for this transistor? Analyze the circuit and find the Q-point (Van Iso). You must show your analytical equations and their solutions.
3. The circuit in the figure below is a 4-R bias circuit for a 4-terminal NMOS transistor.
a. Analyze this circuit and determine the DC Q-point Ins) of the transistor.
b. Perform a DC Bias simulation of this circuit in PSpice. How does the Q-point from your simulation compare with your analytical results in part a?
4. The circuit in the figure below is a basic MOSFET amplifier. Analyze this circuit and determine the following:
a. The DC Q-point (Vos, Ivo) of the transistor
b. The AC small-signal model parameters for the transistor (g., AO.
c. The expected output voltage (both DC and AC components), Vo
d. Perform a Time Domain PSpice simulation of this circuit and show a Probe plot of Vo as a function of time over the range of 0 - 50 ms. How does Vo compare with your analytical results in part c?
5. You are given a PNP transistor with the following bias voltages applied:
Vet; = -0.2 V and Virg = -0.6 V. In which of its four regions does it operate with these biases? What base, collector and emitter currents do you expect if the transistor has the following parameters: Is = 10-10 A,/lp = 166,4 = 3?
6. The NPN transistor in the circuit shown below has the parameters indicated in the PSpice model listing. Analyze this circuit and find the Q-point for the transistor (Vice, /o). You may assume FAR. operation for the transistor, but do NOT assume a value for V,1. Since VAF ( for calculation of the Early effect) is not given in the model, you assume the default condition where VAF = on and the Early effect can be neglected here.
7. The PNP current mirror circuit shown in the figure below is constructed with two identical transistors having the parameters shown in the model listing. Determine the current through the load resistor (RL) to three significant figures. You may assume FAR. operation for the transistor, but make NO assumptions about the emitter-base voltage in this circuit, and don't neglect the Early effect here.
