1 Goal

In this project you will solve a non-trivial design problem explicitly using the divide-and-conquer (D&C) approach. The main reason for using the D&C approach is the ease of the design process and the streamlined nature of the resulting design (e.g., the design has a regular interconnection/wiring pattern) . A typical by- product is a design that also uses less hardware and is generally faster.

Furthermore, the actual design will be implemented and simulated with Quartus II's schematic capture tool using a hierarchical approach-design and simulate smaller components, use them to design and simulate larger components/sub-circuits and so forth until the entire design is completed and simulated. Finally application-specific IC (ASIC) level accurate delay and area (hardware cost) metrics of your design is to be obtained from Synopsys's Design Vision tool.

2 Design Problem-Part 1 of Project 1

64-bit ACL Adder using D&C. Specified in a prior document.

3 Implementation and Simulation using Quartus II

You are required to implement and simulate your gate-based 64-bit ACL adder design obtained in Part 1, as well as, for comparison purposes a 64-bit DAC/CS adder, and a 64-bit RCA using the Quartus II CAD software as specified below:

1. Choose the schematic capture tool in Quartus II to specify your design.

2. Device family to be used for the project is MAX II which is selected by default in Quartus.

3. Design the basic unit(s) using gates. For standard units like muxes, demuxes, full adders (FAs) etc., you can use them if available in the Quartus library, otherwise, you need to also design them using gates. Simulate the basic unit(s) for correctness (generate your own inputs for this simulation; test exhaustively, i.e., using all possible input combinations), save it/them.

4. Using the above saved design(s) and other in-built library components (if any needed) like gates and Mux'es, implement your designed 64-bit ACL adder circuit. In your report, provide the Quartus schematics of all stitch-up and leaf circuits designed, and also of the 64-bit ACL adder circuit. You can provide the schematics in a hierarchical manner. Do the same for the other two adders.

5. Perform timing simulations of the 64-bit ACL adder circuit based on the input vwf file provided by the TA, and determine the maximum output delay you see across all inputs in the timing waveforms (output delay is the time period between the inputs being available and the first time the final correct output appears in a stable way, i.e., without any glitches). Provide screen shots of the timing wave- forms for 4 inputs (and their corresponding outputs) including the maximum output delay one, and show the output delays for each. Do the same for the other two adders.

Also, clearly specify in this part the number of inputs for which you get correct outputs (this is in addition to providing the same statement at the beginning of your report as specified later). Do the same for the other two adders.

Note that this part's scores will mainly reflect the correctness of your design.

4 Conversion to VHDL and Area and Delay Reports from Synopsys's De- sign Vision

First of all , please note that you need to complete this Design Vision (DV) part to get points for the Quartus part, as the Quartus + DV portions form an integrated implementation and analysis portion.

1. Convert the following different levels of the ACL adder circuit schematic to VHDL: 8-bit, 16-bit, 32-bit and 64-bit). Convert only the 64-bit schematic of the other two adders to VHDL.

2. Transfer the VHDL files to the ECE compute server in your directory for this project and use DV as explained in the tutorial session and documentation provided to you to compile the designs (synthesize the circuits) with all efforts set at the "medium" level. Provide all levels of schematics obtained after Design Compilation.

3. Then collect delay (using STA) and area reports (in this case, total area A1 and total cell area A2) for six circuits: 8-bit, 16-bit, 32-bit and 64-bit ACL adders, and 64-bit DAC/CS adder and 64-bit RCA. Provide these three metrics in one table for all six circuits (circuit along rows and metrics along columns). Also include the delay and area reports for all six circuits verbatim in an Appendix at the end of your report..

Comment on the relative differences of the A2 and delay metrics of the three 64-bit adders, and analytically explain whether this is expected or not.

Note that this part's scores will mainly reflect the cost (A2) and speed of your design.

4. Plot the delay (Y axis) versus the number of input bits (X axis) for the four ACL adder circuits: 8- bit, 16-bit, 32-bit and 64-bit, and do a curve fitting of this plot. Include this plot in your report and comment on what this empirical data says about the delay function of a general n-bit ACL adder circuit as a function of n, for n a power of 2.

Also comment on whether and why or why not, this plot is consistent, in terms of order notation (i.e., in terms of the dominating term), with the analytical delay expression you obtained earlier for an n-bit ACL adder.

5. Plot the total cell area A2 (Y axis) versus the number of input bits (X axis) for the four ACL adder circuits: 8-bit, 16-bit, 32-bit and 64-bit, and do a curve fitting of this plot. Include this plot in your report and comment on what this empirical data says about the total cell area function of a general n-bit ACL adder circuit as a function of n, for n a power of 2.

Also comment on whether and why or why not, this plot is consistent, in order notation (i.e., in terms of the dominating term), with the analytical expression you obtained earlier for the total cost of an n-bit ACL adder.

5 Report Preparation and Design File Submissions

You need to submit a clearly written project report detailing all your work including all the steps and re- sults of the design process (discussed in the different parts of the design and Quartus sections), use of the schematic capture tool, simulation results of component(s) and the final design, and other findings, if any, and conclusions.

The report should be professionally written using a text processing software (e.g., MS Word, latex), and all figures, plots, tables, etc. in it should also be generated preferably using some software tool. You should avoid hand-drawn/written material. The report should finally be converted to a pdf file. Finally, to reiterate, just after the report title and team member names, clearly specify the number of inputs for which you get correct outputs (as seen in Quartus's timing simulation).

Along with the report, you'll need to submit all your Quartus design files (using the Archive Project feature) as well as all VHDL files (as a zip or rar file). The TA will send more details on the files to submit. Submit only one set of report plus design files per team.