1. Create 8 bit subtractor in Verilog that uses a 8-bit adder Write a test bench that will test the code with 2 sets of numbers made up of the ASCII Values of the first 2 letters of your first name and the first 2 letters of your last name as the 2 sets of & bit numbers. In each case subtract the 1st letter from the second letter in the test bench and use the $dispLay command to print the results and paste in a screen shot and the code.

2. Write Verilog code for a module called JKFF(JK Flip Flop) that has inputs J, K ClrN, SetN, ClK and outputs Q and QN. Make the gja asynchronous Write a test bench to simulate all combinations of J and K for the single FF. Then create a module that uses 4 instantiations of the JKFF to create a register that can hold 4 bits, but do not write test bench for the 4 bits. Submit code and test bench code.