The text has mentioned two basic designs for FSMs: the Mealy machine and the Moore machine. Figure 4.15 gives a general diagram for a Mealy machine, and figure 6.6 gives a general diagram for a Moore machine. Note that the key difference between the two designs is that in the Mealy machine the outputs are functions of both the current state and the input, whereas in the Moore machine the outputs are functions only of the current state. We wish to investigate the advantages and disadvantages of the two designs. In order to simplify the design process, we shall make the (conservative) assumption that, in general, any output of a block of combinational logic can depend on any input and that there is one maximum propagation-delay parameter (tpdc) for the entire block. That is, none of the outputs of the block can be said to be valid until tpdc after the last input to the block has settled. The timing characteristics of the registers that implement state memory are specified by a setup time t,, a hold time th, and a propagation delay ~,c-Q. For this problem, we assume that t,, th, and t,c-~ are all greater than zero.

A. Which design is likely to require fewer parts to produce?

B. Which design is more flexible, in terms of the values the outputs can take on? Explain. Consider integration of an FSM into a larger system. It is often useful to treat such submodules as monolithic circuit components described by truth tables or state-transition tables plus timing requirements.

C. For each design, draw a timing diagram for the design, including inputs, outputs, current state, next state, and the system clock. Be sure to label all setup times, hold times, and propagation delays. Which of the two designs has the simpler timing specifications? Now consider a larger system composed of some number of FSMs hooked up together. I). In which of these designs can FSMs be hooked up in an arbitrary fashion without violating the dynamic discipline? What is the problem with the other design?

D. In which of these designs can an arbitrarily large number of FSMs be hooked up in series (as in problem 6SF) without our having to worry about the clock period? What is the problem with the other design?