Assignment -
Aim: Design a two-stage inverter circuit shown in Fig.1. The work will initially involve calculating respective dimensions of the different devices within the circuit (i.e. A, B, C and RL), using appropriate equations and parameters/constants provided below. Subsequently, respective layouts for each of the devices, and the overall circuit including interconnects and contact pads, needs to be generated accurately, on scaled or graph paper/s with stipulated scale (e.g. 1µm = 1cm). Make sure to accurately include the alignment error between layouts and utilise minimal area by arranging the layouts appropriately. All dimensions and areas of the layouts must be expressed in terms of the minimum feature size given below.
Description: The circuit in Fig. 1 consists of a two-stage inverter, where the intermediated output from the 1st inverter Vo' feds into the input gate of the 2nd inverter. The input and output of this circuit is Vin and Vout respectively. The driver of both of the inverters consists of enhancement type n-MOS transistors A and B. It can assume that these transistors have the same aspect ratio (W/L), and threshold voltage of 0.3 V.
The load device of the 1st inverter is an (active) saturated n-MOS transistor C, whilst the 2nd inverter has a (passive) implanted resistor load RL. Note the resistance of C can be assumed to be equal to that of RL, and similarly, the resistance of A is identical to the resistance of B, when the transistors are on. However note the dimension of C is not the same as RL since they are different devices. Refer to the p-n junction (passive load) notes to work out dimensions for RL, assuming a sheet resistance for the technology given below.
And to assist you with the calculation for the transistor dimensions, assume a logic 1 input to A, and thus select appropriate value for the intermediate output voltage Vo', to correspond to logic 0. Note this value of Vo' for logic0 needs to be lower than threshold voltage of the driver B so as to ensure that the transistor remains off at logic 0.
Note for the layouts you must take into account the alignment accuracy λa, which can also be assumed to be equal to the minimum feature size or multiple of it. Below are respective parameter values to be used in the calculation:
i. Minimum feature size λm = 0.5 µm
ii. Supply voltage VDD = 5V (Logic 1 input)
iii. Threshold voltage of transistors, VT = 0.3 V
iv. Sheet resistance 150 Ω/square
v. Device constant is given as below; note mobility μ and gate capacitance Co can be assumed to be the same for all transistors.
β = (μCo) W/L = (βo)W/L, where βo = 1.8 x 10-4 AV-2.
Report: Provide a brief description of the circuit operation in Fig. 1. Include all calculations and justification to any assumptions made. Represent all respective individual design layouts for A, B, C and RL, and the overall layout on scaled graph papers, and in terms of the minimum feature size. Use different shading to indicate different regions and include appropriate alignment errors between respective layouts. Make sure to utilise the area effectively particularly on the overall layout where the interconnects and contact pads need to be included.
Useful hints:
1. Initially focus on the first inverter and assume a logic 1 input. Note load C is always on and saturated, whilst with a logic 1 input to the driver A, this transistor is also on, and thus the current flowing between the two devices will be the same. Consequently, using appropriate drain current expressions for the two transistors, determine the ratio of the aspect ratios of the driver to the load. You will need to select appropriate values, ensuring the same ratio is maintained.
2. The resistance values for the two loads are the same i.e. RC = RL. To determine their dimensions i.e. L and W, of the implanted resistor RL, use the given the sheet resistance and consequently calculate the number of squares required.