You are to design a "Serial Sequence Detector". Your design will take in a clock, reset, and a one-bit data signal. Your design will check the input data signal on the rising edge of the input clock. When it finds the sequence "01100110", it will assert an output signal "Found" for one clock cycle. You also need to create a test bench with auto verification. If the design does not assert "Found" when the input sequence is entered, then an ERROR message should be displayed. You should also print a message indicating if the design did work. When creating your test bench, consider outputting the data on the falling edge of clock. This way the rising edge of clock will occur directly in the middle of the data valid window for the incoming data signal.
Deliverables: Draw the State Diagram for your machine using any SW (i.e. MS Visio). 5 Points: Print out your VHDL Code and Simulation waveforms for you design 3 Points: Print out your VHDL Code for your self-checking Test Bench