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A computer has a word-addressable (not byte-addressable) memory consisting of 1M 16-bit words. It also has a 4K-word cache that is 4-way set associative and in which there are 64 words per block. a. Calculate the number of bits in the tag, set index, and block offset fields of the memory address. b. Assume that the cache is initially empty. Suppose that the processor fetches 4352 words from locations 0,1,2,-4351 in that order. It then repeats this fetch sequence 9 more times. If the cache is 10x faster than the main memory, what is the improvement factor resulting from the use of the cache assuming that the LRU algorithm is used for block replacement?

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Computer Engineering, Engineering

Category:- Computer Engineering
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