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We have a 4-way set-associative cache for memory with 32-bit address. The cache has 128 entries. Each block can hold 16 bytes of data. In the following table, fill in the bits of the memory address that are used for Tag and Index.

Tag                                       Index                                   byte offset

                                                                                             3-0

What is the size of the cache, i.e., how many data in the number of bytes can be hold in the cache?

 

Computer Engineering, Engineering

  • Category:- Computer Engineering
  • Reference No.:- M9887510

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