The project consists of multiple phases. It is to develop a logic analyzer and waveform viewer (LA/WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports both analog and digital channels, with one-level triggering.

Project:

Add a data source emulator to the minimal system. When requested by the FPGA board, the microprocessor board sends one channel of N digitized analog samples and one channel of N digital samples to the PC. (N is a constant to be determined in the lab and the coding should allow N to be changed easily.) The PC application will then graphically display the data. The digitized analog data come from the ADC on the microprocessor board and the incoming analog signal comes from a voltage divider based on a force-sensitive-resistor. The digital samples can be derived from the digitized analog data. For example, the digital value is one if and only if the analog value is more than a threshold.. Use Visuall C++ for host programming and verilog for FPGA...Please help me with this.