The MP has a limited set of instructions, however provides enough capabilities to control a microwave oven or some other consumer appliances.MP can access 64Kx8 memory. Inputting/outputting data from the microwave keypadand displaying them at the oven's display are considered memory accesses.So, memory mapped input/output is not supported by input/output instructions, rather memory access instructions are used (similar to SRC).
The MP has only one 8-bit general purpose register, R, and Accumulator Register, AC. There is 1-bit zero flag,Z . It is set to 1, if the result of any arithmetic or logic instruction is 0. This is done automatically by hardware. Otherwise, it is set to 0.
There are some registers which are not a part of the instruction set, but architected to support temporal storage and buffers for data and address storage (see, later in this description).
Table below has a complete description of the instruction set.
It can be seen that instruction code (opcode) is 8-bit long although there are only 16 instructions in the set. This is done for future extension of the set and for the ease of control and decoding.As the upper 4-bits are zeros for all opcodes, instructions are decoded only for low order 4 bits. Here Γ indicates a 16-bit memory address. This means that memory access instructions are 3- byte long, where Byte #1 is an opcode, Byte #2 is the low order byte of Γ and byte #3 is the high order byte of Γ. Other instructionsare 1- byte instructions.
Additional registers are:
A 16-bit Address register, AR (similar to MA of SRC) which supplies address to the memory A[15..0].
A 16-bit program counter, PC contains the address of the instruction to be fetched, or the address of the next required operand of the
instruction.
An 8-bit Instruction register, IR is dedicated to instruction opcodes only.
An 8-bit data register, DR (similar to MD of SRC) receives instructions and data from the memory and transfers data to the memory via D[7..0] which are 8 bi-directional pins.
An 8-bit temporary register TRis a buffer for temporarily storing data, addresses during the execution.
The figure below(left) shows the architecture. Although some registers are 8-bit registers, and data are 8-bit, the bus is made for 16 bits to accommodate 16-bit addresses in PC and AR.
Figure:Datapath
All arithmetic operations are implemented on R and AC registers. The ALU architecture is provided below with a parallel adder (CLA, one level is affordable) and a simple logic for logic operations.
Figure: ALU
The Control Unit (see, below) has a decoder which takes opcodes and outputs instruction types (left) and the Control step decoder(right) similar to SRC's control. From the figure, it follows that the maximum number of cycles is 8.
Assignment
1) Write concrete RTN and control signals for all instructions in the instruction set
2) Design Logic for the control unit
3) Implement, simulate and test on actual instructions
Extra credit:
Several modifications can be made for optimizing the design (reducing number of cycles and cost). Among these modifications the following is to be considered:
4) Direct paths between certain pairs of registers
5) Use of two buses for different paths and connect buses
6) Special way of connecting registers to a single bus.